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is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 1 1mx18 , 512kx36 18mb quad (burst 2 ) synchronous sram features ? 512kx36 and 1mx18 configuration available. ? on - chip delay - locked l oop (dll) for wide data valid window. ? separate independent read and write ports with concurrent read and write operations. ? syn chronous pipeline read with early write operation. ? double data r ate (ddr) interface for read and write input ports. ? fixed 2 - bit burst for read and write operations. ? clock stop support. ? two input clocks (k and k#) for address and control registering at risi ng edges only. ? two output clocks (c and c#) for data output control. ? two echo clocks (cq and cq#) that are delivered simultaneously with data. ? +1.8v core power supply and 1.5, 1.8v vddq, used with 0.75, 0.9v vref. ? hstl input and output levels. ? registered addresses, write and read controls, byte writes, data in, and data outputs. ? full data coherency. ? boundary scan using limited set of jtag 1149.1 functions. ? byte write capability. ? fine ball grid array (fbga) package: 1 3 mmx1 5 mm and 15mmx17mm body size 165 - bal l (11 x 15) array ? programmable impedance output drivers via 5x user - supplied precision resistor. description the and are synchronous, high - performance cmos static random access memory (sram) devices. these srams have separate i/os, eliminating the need for high - speed bus turnaround. the rising edge of k clock initiates the read/write operation, and all internal operations are self - timed. refer to the for a description of the bas ic operations of these srams. the input address bus operates at double data rate. the following are registered internally on the rising edge of the k clock: ? read address ? read enable ? write enable ? byte writes ? data - in for early writes the following are registered on the rising edge of the k# clock: ? write address ? byte writes ? data - in for second burst addresses byte writes can change with the corresponding data - in to enable or disable writes on a per - byte basis. an internal write buffer enab les the data - ins to be registered half a cycle earlier than the write address. the first data - in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the k# clock. during the burst r ead operation, the data - outs from the first bursts are updated from output registers of the second rising edge of the c# clock (starting 1.5 cycles later after read command). the data - outs from the second bursts are updated with the third rising edge of th e c clock. the k and k# clocks are used to time the data - outs whenever the c and c# clocks are tied high. the device is operated with a single +1.8v power supply and is com patible with hstl i/o interface s . copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without no tice. issi assumes no liability arising out of the application or use of any in formation, products or services described herein. customers are advised to obtain the latest version of this device spec ification before relying on any published information and before placing orders for products. integrated silicon solution, inc. does no t recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. pr oducts are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liabil ity of integrated silicon solution, inc is adequately protected under the circumstances novem ber 20 14
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 2 package ballout and description x36 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# nc/sa 1 nc/sa 1 w# bw 2 # k# bw 1 # r# nc/sa 1 nc/sa 1 cq b q27 q18 d18 sa bw 3 # k bw 0 # sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v d dq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff# v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi note s: the following ba lls are reserved for higher densities: 9a for 36m, 3a for 72 mb, 1 0a for 144mb, and 2a for 288mb. x18 fbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq# nc/sa 1 nc/sa 1 w# bw 1 # k# nc/sa 1 r# sa nc/sa 1 cq b nc q9 d9 sa nc k bw 0 # sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff# v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi note s: 1. the following balls are reserved for higher densit ies: 3a for 36m, 10a for 72mb, 2a for 144mb , and 7a for 288m b .
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 3 ball descriptions symbol type description k, k# input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k # . k # is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock r ising edges. these balls cannot remain vref level. c, c# input input clock for output data. c and c# are used to clock out the read data. they can be used together to deskew the flight times of various devices on the board back to the controller. see appl ication example for further details. cq, cq# output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tri - states. doff# input dll disable and reset input : when low , this input causes the dll to be bypassed and reset the previous dll information. when high, dll will start operating and lock the frequency after tck lock time. the device behaves in 1.0 read latency mode when the dll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz . sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k . these inputs are ignored when device is deselected. d0 - d n input synchronous data inputs: input data must meet setup and hold times around the rising edges of k and k # during write operations. see ball configuration figures for ball site location of individual signals. the x 18 device uses d0~d17. d18~d35 should be treated as nc pin. the x 36 device uses d0~d35. q0 - q n output synchronous data outputs: output data is synchronized to the respective c and c # , or to the respective k and k # if c and /c are tied to h igh. this bus operates in response to r # commands. see ball configuration figures for ball site location of individual signals. the x 18 device uses q0~q17. q18~q35 should be treated as nc pin. the x 36 device uses q0~q35. w# input synchronous write: when l ow, this input causes the address inputs to be registered and a write cycle to be initiated. this input must meet setup and hold times around the rising edge of k . r# input synchronous read: when low, this input causes the address inputs to be registered and a read cycle to be initiated. this input must meet setup and hold times around the rising edge of k . bw x # input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and # k for each of the two rising edges comprising the write cycle. see write truth table for signal to data relationship. v ref input r eference hstl input reference voltage: nominally vddq/2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. v dd power power supply: 1.8 v nominal. see dc characteristics and operating conditions fo r range. v ddq power power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operating conditions for range. v ss ground ground of the device zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2 x rq, where rq is a resistor from this ball to ground. this ball can be connected directly to vddq, which enables the minimum impedance mode. this ball cannot be connected dir ectly to vss or left unconnected. tms, tdi, tck input ieee1149.1 input pins for jtag . tdo out put ieee1149.1 out put pins for jtag . nc n/a no connect: these signals should be left floating or connected to ground to improve package heat dissipation.
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 4 sram features description block diagram note: numerical values in parentheses refer to the x18 device configuration . read operations the sram operates continuously in a burst - of - two mode. read cycles are started by registering r # in active low state at the rising edge of the k clock. a second set of clocks, c and c # , are used to control the timing to the outputs. a set of free - running echo clocks, cq and cq # , are produced internally with timings identical to the data - outs. the echo clocks can be used as data capture clocks by the receiver device. when the c and c # clocks are connected high, then the k and k # clocks assume the function of those clocks. in this case, the data corresponding to the first address is clocked 1.5 cycl es later by the rising edge of the k # clock. the data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the k clock. a nop operation (r # is high) does not terminate the previous read. write operations write opera tions can also be initiated at every rising edge of the k clock whenever w # is low. the write address is provided 0.5 cycles later, registered by the rising edge of k# . again, the write always occurs in bursts of two . the write data is provided in a n ear ly write mode; that is, the data - in corresponding to the first address of the burst, is presented 0.5 cycle s before the rising edge of the following k clock. the data - in corresponding to the second write burst address follows next, registered by the risin g edge of k # . the data - in provided for writing is initially kept in write buffers. the information in these buffers is written into the array on the third write cycle. a read cycle to the last write address produces data from the write buffers. similarly , a read address followed by the same write address produces the latest write data. the sram maintains data coherency. d a t a r e g i s t e r a d d r e s s r e g i s t e r c o n t r o l l o g i c d ( d a t a - i n ) 3 6 ( 1 8 ) 1 8 ( 1 9 ) a d d r e s s 4 ( 2 ) r # w # b w x # c l o c k g e n e r a t o r k 5 1 2 k x 3 6 ( 1 m x 1 8 ) m e m o r y a r r a y w r i t e d r i v e r a d d r e s s d e c o d e r s e n s e a m p l i f i e r s s e l e c t o u t p u t c o n t r o l o u t p u t r e g i s t e r 1 8 ( 1 9 ) 3 6 ( 1 8 ) 3 6 ( 1 8 ) 7 2 ( 3 6 ) 7 2 ( 3 6 ) o u t p u t s e l e c t 3 6 ( 1 8 ) q ( d a t a - o u t ) c q , c q # ( e c h o c l o c k s ) 2 o u t p u t d r i v e r c k # c # d o f f #
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 5 during a write, the byte writes independently control which byte of any of the four burst addresses is written (see x18/x36 write truth tables and timing reference diagram for truth table ). whenever a write is disabled (w # is high at the rising edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 results in a driver impedance of 50. the allowable range of rq to gua rantee impedance matching is between 175 and 350 with v ddq =1.5v. the rq resistor should be placed less than two inches away from the zq ball on the sram module. the capacitance of the loaded zq trace must be less than 7.5 pf. the zq pin can also be direc tly connected to v ddq to obtain a minimum impedance setting. zq must never be connected to v ss . p rogrammable impedanc e and power - up requirement s periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drif ts in supply voltage and temperature. at power - up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 1024 clock cycles. single clock mode this device can be also operated in single - clock mod e. in this case, c and c# are both connected high at power - up and must never change. under this condition, k and k# will control the output timings. either clock pair must have both polarities switching and must never connect to v ref , as they are not diff erential clocks. depth expansion separate input and output ports enable easy depth expansion, as each port can be selected and deselected independently. read and write operations can occur simultaneously without affecting each other. also, all pending read and write transactions are always completed prior to deselecting the corresponding port . delay lock ed loop (dll) delay lock ed loop (dll) is a new system to align the output data coincident with clock rising or falling edge to enhance the output valid timi ng characteristics . it is locked to the clock frequency and is constantly adjusted to match the clock frequency . t herefore device can have stable output over the temperature and voltage variation . dll has a limitation of locking range and jitter adjustmen t which are specified as tkhkh and tkcvar respectively in the ac timing characteristics. in order to turn this feature off, applying logic low to the doff# pin will bypass this. in the dl l off mode, the device behaves with 1.0 cycle latency and a longer ac cess time which is known in ddr - i or old quad mode. the dll can also be reset without power down by toggling doff# pin low to high or stopping the input clocks k and k# for a minimum of 30ns.(k and k# must be stayed either at higher than vih or lower than vil level. remaining vref is not permitted.) dll reset must be issued when power up or when clock frequency changes abruptly . after dll being reset, it gets locked after 2048 cycles of stable clock.
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 6
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 7 power - up and power - down sequences the recommendati on of voltage apply sequence is : v dd v ddq 1) v ref 2) v in notes: v ddq can be applied concurrently with v dd . v ref can be applied concurrently with v ddq . after power and clock signals are stabilized, device can be ready for normal operation after tkc - lock cycles. in tkc - lock cycle period, dev ice initializes internal logics and locks dll. depending on /doff status, locking dll will be skipped. the following timing pictures are possible examples of power up sequence. sequence1. /doff is fixed low after tkc - lock cycle of stable clock, device is ready for normal operation. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. sequence2. /doff is controlled and goes high after clock being stable. note) all i nputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. >tkc - lock for device initialization >tkc - lock for device initialization power on stage unstable clock period stable clock period read to use k k# vdd vddq vref vin power on stage unstable clock period stable clock period read to use k k# doff# vdd vddq vref vin
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 8 sequence3. /doff is controlled but goes high before clock being stable. because dll has a risk to be locked with the unstable clo ck, dll needs to be reset and locked with the stable input. a) k - stop to reset. if k or k# stays at vih or vil for more than 30ns, dll will be reset and ready to re - lock. in tkc - lock period, dll will be locked with a new stable value. device can be ready for normal operation after that. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. a) /doff low to reset. if /doff toggled low to high, dll will be reset and r eady to re - lock. in tkc - lock period, dll will be locked with a new stable value. device can be ready for normal operation after that. note) applying dll reset sequences (sequence 3a, 3b) are also required when operating frequency is changed with out power off. note) all inputs including clocks must be either logically high or low during power on stage. timing above shows only one of cases. > 30ns >tkc - lock for device initialization > tdoffl owtoreset >tkc - lock for device initialization power on stage unstable clock period k-stop stable clock period read to use k k# doff# vdd vddq vref vin power on stage unstable clock period doff reset dll stable clock period read to use k k# doff# vdd vddq vref vin
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 9 application example in the following application example, the second pair of c and c# clocks is delayed s uch that the return data meets the data setup and hold times at the memory controller. s a d r # w # b w x # k k # q c q c q # z q r q = 2 5 0 d a t a - i n d a t a - o u t a d d r e s s s r a m # 1 c q i n p u t s r a m # 1 c q # i n p u t s r a m # 4 c q i n p u t s r a m # 4 c q # i n p u t r e a d c o n t r o l w r i t e c o n t r o l b y t e w r i t e c o n t r o l s o u r c e c l k r e t u r n c l k m e m o r y c o n t r o l l e r v t r r = 5 0 v t = v r e f s o u r c e c l k # r e t u r n c l k # c c # s r a m # 1 s a d r # w # b w x # k k # q c q c q # z q r q = 2 5 0 c c # s r a m # 4 v t r v t r v t r v t r
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 10 state diagram notes: 1. internal burst counter is fixed as two - bit linear; that is when first addres s is a0+0, next internal burst addresses are a0+1. 2. read refers to read active status with r # = low . read # refers to read inactive status with r # = high . 3. write refers to write active status with w # = low . write # refers to write inactive status with w # = hig h . 4. the read and write state machines can be active simultaneously. 5. state machine control timing sequence is controlled by k. p o w e r - u p r e a d n o p w r i t e n o p l o a d n e w r e a d a d d r e s s l o a d n e w w r i t e a d d r e s s d d r r e a d d d r w r i t e r e a d # w r i t e # r e a d w r i t e r e a d w r i t e a l w a y s ( f i x e d ) a l w a y s ( f i x e d ) w r i t e # r e a d #
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 11 timing reference diagram for truth table the timing reference diagram for truth table is helpful in understanding the clock and w rite truth tables , as it shows the cycle relationship between clocks, address, data in, data out, and control signals . read command is issued at the beginning of cycle t. write command is issued at the beginning of cycle t+1. clock truth table (use the following table with the .) mode clock controls data in data out k r# w# d b d b+1 q a q a+1 stop clock stop x x previous state previous state previous state previous state no operation (nop) l h h h x x high - z high - z read a l h l x x x d out at c# (t+ 1 .5) d out at c (t+ 2 .0) write b l h x l d in at k (t) d in at k# (t+0 .5) x x notes: 1. internal burst counter is always fixed as two - bit. 2. x = dont care; h = logic 1; l = logic 0. 3. a read operation is started when control signal r # is active low 4. a write operation is started when control signal w # is active low. d b d b + 1 d d d d + 1 q a q a + 1 q c q c + 1 t + 1 t t + 2 t + 3 t + 4 t + 5 a c c y c l e k c l o c k k # c l o c k r # w # b w x # a d d r e s s d a t a - i n d a t a - o u t c c l o c k c # c l o c k c q c l o c k c q # c l o c k b d
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 12 5. for timing definitions, refer to the ac timing characteristics t able . signals must meet ac specifications at timings indicat ed in parenthesis with respect to switching clocks k , k # , c and c # . x18 write truth table (use the following table with the timing reference diagram for truth table .) operation k (t) k# (t+0.5) bw 0 # bw 1 # d b d b+1 write byte 0 l h l h d0 - 8 (t ) write byte 1 l h h l d9 - 17 (t) write all bytes l h l l d0 - 17 (t) abort write l h h h don't care write byte 0 l h l h d0 - 8 (t+0 .5) write byte 1 l h h l d9 - 17 (t+0 .5) write all bytes l h l l d0 - 17 (t+0 .5) abort write l h h h don't care notes: 1. refer to the timing reference diagram for truth table . cycle time starts at n and is referenced to the k clock. 2. for all cases, w # needs to be active low during the rising edge of k occurring at tim e t. 3. for timing definitions refer to the ac timing characteristics table. signals must meet ac specifications with respect to switching clocks k and k # . x36 write truth table (use the following table with the timing reference diagram for truth table .) oper ation k (t) k# (t+0.5) bw 0 # bw 1 # bw 2 # bw 3 # d b d b+1 write byte 0 l h l h h h d0 - 8 (t ) write byte 1 l h h l h h d9 - 17 (t ) write byte 2 l h h h l h d18 - 26 (t ) write byte 3 l h h h h l d27 - 35 (t ) write all bytes l h l l l l d0 - 35 (t ) abort write l h h h h h don't care write byte 0 l h l h h h d0 - 8 (t +0.5 ) write byte 1 l h h l h h d9 - 17 ( t +0.5 ) write byte 2 l h h h l h d18 - 26 ( t +0.5 ) write byte 3 l h h h h l d27 - 35 ( t +0.5 ) write all bytes l h l l l l d0 - 35 ( t +0.5 ) abort write l h h h h h don't care notes: 1. for all c ases, w # needs to be active low during the rising edge of k occurring at time t. 2. for timing definitions refer to the ac timing characteristics table. signals must meet ac specifications with respect to switching clocks k and k # .
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 13 el ectrical specifications absolute maximum ratings parameter symbol min max units power supply voltage v dd ? 0. 5 2.9 v i/o power supply voltage v ddq ? 0.5 2.9 v dc input voltage v in ? 0.5 v dd + 0.3 v data out voltage v dout ? 0.5 2.6 v junction temperature t j - 110 c storage tempe rature t stg ? 55 + 125 c note: stresses greater than those listed in this table can cause permanent damage to the device. this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the ope rational sections of this datasheet is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . operating temperature range temperature range symbol min max units commercial t a 0 +70 c industrial t a ? 40 + 85 c dc electrical characteristics (over the operating t emperature range, v dd =1.8v 5% ) parameter symbol min max units notes x36 average power supply operating current (i out =0, v in =v ih or v il ) i dd30 i dd33 i dd40 ? 1100 1000 900 ma 1, 2 x18 average pow er supply operating current (i out =0, v in =v ih or v il ) i dd30 i dd33 i dd40 ? 1050 95 0 85 0 ma 1, 2 power supply standby current (r#=v ih , w#=v ih . all other inputs=v ih or v i l , i ih =0) i sb30 i sb33 i sb40 ? 440 420 390 ma 1 ,2 input leakage current ( 0 v in v d dq fo r all input balls except v ref , zq, tck, tms, tdi ball) i li ? 2 +2 a 3 output leakage current ( 0 v out v d dq for all output balls except tdo ball; output must be disabled. ) i lo ? 2 +2 a output high level voltage (i oh = - 0.1 ma , zqnorm ) v oh v ddq ? 0. 2 v ddq v output low level voltage (i ol =+ 0.1 ma , zqnorm ) v ol v ss v ss +0. 2 v notes: 1. i out = chip output current. 2. the numeric suffix indicates the part operating at speed, as indicated in (that is, i dd25 indicates 2.5ns cycle time ). 3. doff# ball do es not follow this spec, i li = 100ua
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 14 recommended dc operating conditions ( over the operating t emperature range) parameter symbol min typical max units notes supply voltage v dd 1.8 C 5% 1. 8 1.8+5% v 1 output driver supply voltage v ddq 1.4 1.5 v dd v 1 input high voltage v ih v ref +0.1 - v ddq +0.2 v 1, 2 input low voltage v il C 0.2 - v ref C 0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.95 v 1, 5 clock signal voltage v in - clk C 0.2 - v ddq +0.2 v 1, 4 notes: 1. all voltages are referenced to v ss . all v dd , v ddq , and v ss pins must be connected. 2. v ih (m ax) ac = see . 3. v il (m in) ac = see . 4. v in - clk specifies the maximum allowable dc excursions of each clock (k, k # , c, and c# ). 5. peak - to - peak ac component superimposed on v ref may not exceed 5% of v ref . overshoot and undershoot timings 2 0 % m i n c y c l e t i m e v d d q v d d q + 0 . 6 v v i h ( m a x ) a c o v e r s h o o t t i m i n g 2 0 % m i n c y c l e t i m e g n d g n d - 0 . 6 v v i l ( m i n ) a c u n d e r s h o o t t i m i n g
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 15 typical ac input characteristics parameter symbol min max units notes ac input logic high v ih ( ac ) v ref + 0.2 v 1 , 2, 3, 4 ac i nput logic low v il ( ac ) v ref C 0.2 v 1, 2, 3, 4 clock input logic high v ih - clk ( ac ) v ref + 0.2 v 1, 2, 3 clock input logic low v il - clk ( ac ) v ref C 0.2 v 1, 2, 3 notes: 1. the peak - to - peak ac component superimposed on v ref may not exceed 5% of the dc componen t of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the diagram. 4. see the diagram. the signals should swing monotonically with no steps rail - to - rail with input signals never ringing back pa st v ih (ac) and v il (ac) during the input setup and input hold window. v ih (ac) and v il (ac) are used for timing purposes only. ac input definition pbga thermal characteristics parameter symbol 13x15 bga 15x17 bga units therm al resistance ( junction to ambient at airflow = 1m/s) r ja 19.6 18.0 c/w thermal resistance ( junction to pins ) r jb 4.02 3.30 c/w thermal resistance ( junction to case ) r jc 4.53 4.20 c/w note: these parameter s are guaranteed by design and tested by a sample basis only. k # v r e f k v r a i l v i h ( a c ) v r e f v i l ( a c ) v - r a i l s e t u p t i m e h o l d t i m e
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 16 pin capacitance parameter symbol test condition max units input or output capacitance except d and q pins c in , c o 5 pf d and q capacitance (d0 C d x, q0 - qx ) c dq 6 pf clocks capacitance (k , k, c, c) c clk 4 pf note: these parameter s are guaranteed by design and tested by a sample basis only. programmable impedan ce output driver dc electrical character istics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter sym bol min max units notes output logic high voltage v oh v ddq /2 - 0.12 v ddq /2 + 0.12 v 1, 3 output logic low voltage v ol v ddq /2 - 0.12 v ddq /2 + 0.12 v 2, 3 notes: 1. 2. 3. parameter tested with rq=250 and v ddq =1.5v ac test conditions (over the operating temperature range, v dd =1.8v 5% ) parameter symbol conditions units notes output drive power supply voltage v ddq 1.5 v 2 input logic high voltage v ih 1.25 v input logi c low voltage v il 0.25 v input reference voltage v ref 0.75 v input rise time t r 2 v/ ns input fall time t f 2 v/ ns output timing reference level v ddq /2 v clock reference level 0.75 v output load conditions 1, 2 note s : 1. see ac test loading. 2. parameters are tested with rq=250 and vddq=1.5v, but issi devices are able to support v ddq =1.4v to v dd ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq oh ? ? ? ? ? ? ? ? ? ? ? ? ? 5 rq 2 v | i | ddq ol
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 17 ac test loading (a) unless otherwise noted, ac test loading assume this condition. (b) tchqz and tchqx1 are specified with 5pf load c apacitance and measured when transition occurs 100mv from the steady state voltage. (c)tdo 5 0 v r e f t e s t c o m p a r a t o r o u t p u t 5 0 v r e f v r e f 1 0 0 m v t e s t c o m p a r a t o r 5 0 5 p f v r e f o u t p u t v r e f t e s t c o m p a r a t o r o u t p u t 5 0 2 0 p f 5 0 v r e f
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 18 ac timing characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) para meter symbol 30 ( 333 mhz) 33 (300mhz) 40 ( 250 mhz) unit notes min max min max min max clock clock cycle time (k, k #,c,c# ) tkhkh 3.00 8.4 3.33 8.4 4.00 8.4 ns clock phase jitter (k, k #,c,c# ) tkc var 0. 3 0.3 0.3 ns 4 clock high ti me (k, k #,c,c# ) tkhkl 0.4 0.4 0.4 cycle clock low time (k, k #,c,c# ) tklkh 0.4 0.4 0.4 cycle clock to clock (k h k# h , c h c# h ) tkhk # h 1.35 1.50 1.80 ns clock to data clock (k > c, k# > c#) tkhch 0 1. 3 5 0 1. 48 0 1.8 ns dll lock time (k ,c ) tkc lock 1024 1024 1024 cycles 5 doff low period to dll reset tdofflowtoreset 5 5 5 ns k static to dll reset tkcreset 30 30 30 ns output times c , c# high to output valid tchqv 0.45 0.45 0.45 ns 1,3 c , c# high to output hold tchqx - 0.45 - 0.45 - 0.45 ns 1,3 c , c# high to echo clock valid tchcqv 0.45 0.45 0.45 ns 1 c , c# high to echo clock hold tchcqx - 0.45 - 0.45 - 0.45 ns 1 cq, cq # high to output valid tcqhqv 0.30 0.30 0.30 ns 1,3 cq, cq # high to output hold tcqhqx - 0.30 - 0.30 - 0.30 ns 1,3 c,c# high to output high - z tchqz 0.45 0.45 0.45 ns 1,3 c,c# high to output low - z tchqx1 - 0.45 - 0.45 - 0.45 ns 1,3 setup times address valid to k rising edge tavkh 0.3 0 0.3 0 0.3 0 ns 2 r#,w# c ontrol inputs valid to k rising edge tivkh 0.3 0 0.3 0 0.3 0 ns 2 bw x # c ontrol inputs valid to k rising edge tivkh 2 0.3 0 0.3 0 0.3 0 ns 2 data - in valid to k, k # rising edge tdvkh 0.3 0 0.3 0 0.3 0 ns 2 hold times k rising edge to address hold tkhax 0.3 0 0.3 0 0.3 0 ns 2 k rising edge to r#,w# control inputs hold tkhix 0.3 0 0.3 0 0.3 0 ns 2 k rising edge to bw x # control inputs hold tkhix 2 0.3 0 0.3 0 0.3 0 ns 2 k, k # rising edge to data - in hold tk hdx 0.3 0 0.3 0 0.3 0 ns 2 notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. during normal operation, vih, vil, trise, and tfall of inputs must be within 20% of vih, vil, trise, and tfall of clock. 3. if c, c are tied high, then k, k become the references for c, c timing parameters. 4. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 6. the data sheet parameters reflect tester guard bands and test setup variations. 7. to avoid bus contention, at a given voltage and temperature tchqx1 is bigger than tchqz. the specs as shown do not imply b us contention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a max parameter (worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different v oltage and temperature.
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 19 read, write, and nop timing diagram notes: 1. if address a1 = a2, data q1 - 1 = d2 - 1 and data q1 - 2 = d2 - 2. write data is forwarded immediately as read results. 2. b2 - 1 and b2 - 2 refer to all bwx # byte controls for d2 - 1 and d2 - 2 respectively. 3. b4 - 1 and b4 - 2 refer to all bwx# byte controls for d4 - 1 and d4 - 2 respectively. 4. b6 - 1 and b6 - 2 refer to all bwx# byte controls for d6 - 1 and d6 - 2 respectively. 5. b7 - 1 and b7 - 2 refer to all bwx# byte controls for d7 - 1 and d7 - 2 res pectively. 6. outputs are disabled one cycle after a nop . k c l o c k k # c l o c k a d d r e s s ( s a ) r # w # b w x # d a t a - i n ( d ) 1 2 3 4 5 6 7 t k h k h t k h k l t k l k h t k h k # h t a v k h t k h a x t i v k h t k h i x d a t a - o u t ( q ) t c h q x 1 t c h q v t c q h q x t c h c q x t c h c q v t c q h q v t k h k h t k h k l t k l k h t k h k # h c c l o c k c # c l o c k c q c l o c k c q # c l o c k u n d e f i n e d d o n t c a r e t k h c h r e a d w r i t e n o p r e a d w r i t e r e a d w r i t e w r i t e t i v k h t k h i x d 2 - 1 d 2 - 2 d 4 - 1 d 4 - 2 t d v k h t k h d x d 6 - 1 d 6 - 2 d 7 - 1 d 7 - 2 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 2 - 1 b 2 - 2 b 4 - 1 b 4 - 2 b 6 - 1 b 6 - 2 b 7 - 1 b 7 - 2 t c h q z q 1 - 3 q 1 - 2 q 1 - 1 q 1 - 4 q 3 - 2 q 3 - 1 t c h q x
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 20 ieee 1149.1 serial boundary scan of jtag these srams incorporate a serial boundary scan test access port (tap) controller in 165 fbga package. that is fully compliant with ieee standard 1149.1 - 2001. the tap controller operates using standard 1.8 v interface logic levels. disabling the jtag feature these srams operate without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tm s are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device . test access port signal list: test clock (tck) the test clock is to operate only tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is to se t commands of the tap controller and is sampled on the rising edge of tck. this pin can be left unconnected at sram operation. the pin is pulled up internally to keep logic high level. test data - in (tdi) the tdi pin is to receive serially input informatio n into the instruction and data registers. it can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register (refer to the tap controller state diagram ) . tdi is internally pulled up and can be unconnected at sram. tdi is connected to the most significant bit (msb) on any register. test data - out (tdo) the tdo pin is to drive serially clock data out from the jtag registers. the output is active, depending upon the current state of the tap state machine (refer to instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register.
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 21 tap contro ller state and block diagram tap controller state machine b y p a s s r e g i s t e r ( 1 b i t ) i d e n t i f i c a t i o n r e g i s t e r ( 3 2 b i t s ) i n s t r u c t i o n r e g i s t e r ( 3 b i t s ) t a p c o n t r o l l e r t d o t m s t c k t d i c o n t r o l s i g n a l s b o u n d a r y s c a n r e g i s t e r ( 1 0 9 b i t s ) . . . t e s t l o g i c r e s e t s e l e c t d r r u n t e s t i d l e 0 1 1 c a p t u r e d r 0 1 0 0 1 0 1 1 0 s h i f t d r e x i t 1 d r p a u s e d r e x i t 2 d r 1 1 u p d a t e d r 0 s e l e c t i r 1 c a p t u r e i r 0 1 0 0 1 0 1 s h i f t i r e x i t 1 i r p a u s e i r e x i t 2 i r 1 1 u p d a t e i r 0 0 0 1 0 1 0
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 22 performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the opera tion of the sram and can be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state . tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction regist er this register is loaded during the update - ir state of the tap controller. three - bit instructions can be serially loaded into the instruction register. at power - up, the instruction register is loaded with the idcode instruction. it is also loaded with th e idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture - ir state, the two lsbs are loaded with a binary 01 pattern to allow for fault isolation of the board - level s erial test data path. bypass register the bypass register is a single - bit register that can be placed between the tdi and tdo balls. it is to skip certain chips without serial boundary scan. this allows data to be shifted through the sram with minimal del ay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output balls on the sram . several no connected(nc) balls are also included in the scan re gister to reserve other product options. the boundary scan register is loaded with the contents of the sram input and output ring when the tap controller is in the capture - dr state and is then placed between the tdi and tdo balls when the controller is mov ed to the shift - dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. each bit corresponds to one of the balls on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor - specific, 32 - bit code during the capture - dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and c an be shifted out when the tap controller is in the shift - dr state . the id register has a vendor id code and other information tap instruction set tap instruction set is available to set eight instructions with the three bit instruction register and all co mbinations are listed in the tap instruction code table. three of listed instructions on this table are reserved and must not be used. instructions are loaded serially into the tap controller during the shift - ir state when the instruction register is place d between tdi and tdo. to execute an instruction once it is shifted in, the tap controller must be moved into the update - ir state. idcode the idcode instruction causes a vendor - specific, 32 - bit code to be loaded into the instruction register. it also plac es the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift - dr state. the idcode instruction is loaded into the instruction register upon power - up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift - dr state. the sample z command puts the output bus into a high z sta te until the next command is supplied during the update ir state.
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 23 sample/preload sample/preload is a ieee 1149.1 basic instruction which connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift - dr state.. a sn apshot of data on the inputs and output balls is captured in the boundary scan register when the tap controller is in a shift - dr state . the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture - dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition. t his will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time . the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still po ssible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift - dr state. this places the boundary s can register between the tdi and tdo balls. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selecti on of another boundary scan test operation. the shifting of data for the sample and pre load phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift - dr state, th e bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. private do not use these instructions. they are reserved for futur e use and engineering mode. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift - dr controller state. i eee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri - state mode. the boundary scan register has a special bit located at bit #109. when this scan cell, called the extest output bus tri - state, is latched into the p reload register during the update - dr state in the tap controller, it directly controls the state of the output (q - bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell during the shift - dr state. during update - dr, the value loaded into that shift - reg ister cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q - bus pins. by default, it places q in high - z. the actual transfer occurs during the update ir state after extest is loaded . the val ue of the internal register can be changed during sample and extest only. jtag dc operating characteristics (over the operating temperature range , v dd =1.8v5% ) parameter symbol min max units notes jtag input high voltage v ih1 1.3 v dd +0.3 v jtag input lo w voltage v il1 C oh1 1.4 - v |i oh1 | = 2ma jtag output low voltage v ol1 - 0.4 v i ol1 = 2m a jtag output high voltage v oh 2 1.6 - v |i oh 2 | =100u a jtag output low voltage v ol 2 - 0. 2 v i ol 2 =100ua jtag input leakage current i li jtag - 100 +100 ? 0 vin vdd lojtag - 5 +5 ? 0 vout vdd notes: 1. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible .
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 24 jtag ac test conditi ons (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v jtag ac characteristics (over the operating temperature range, v dd =1.8v5%, v ddq =1.5v/1.8v ) parameter symbol min max units tck cycle time t thth 50 C thtl 20 C tlth 20 C mvth 5 C thmx 5 C dvth 5 C thdx 5 C cvth 5 C thcx 5 C tlov C tlqx 0 C note: see ac test loading (c) jtag ti ming diagram t c k t m s t t h t h t t h t l t t l t h t t h m x t m v t h t d i t d o t t l o v t t h d x t d v t h t t l o x
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 25 instruction set code instruction tdo output 000 extest boundary scan register 001 idcode 32 - bit identification register 010 sample - z boundary scan register 011 private do not use 100 sample (/preload) boundar y scan register 101 private do not use 110 private do not use 111 bypass bypass register id register definition revision number (31 :29) part configuration (28:12) vendor id code (11:1) start bit (0) 000 0 t def0wx0 1p q l b t s0 00011010101 1 part configu ration definition: 1. def = 001 for 18mb, 010 for 36mb , 011 for 72mb 2. wx = 11 for x36, 10 for x18 3. p = 1 for ii+(quad - p/ddr - iip) , 0 for ii(quad/ddr - ii) 4. q = 1 for quad, 0 for ddr - ii 5. l = 1 for rl=2.5, 0 for rl 2.5 6. b = 1 for burst of 4, 0 for burst of 2 7. s = 1 for separate i/o, 0 for common i/o 8. t = 1 for odt option, 0 for no odt option
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 26 boundary scan exit order order pin id order pin id order pin id 1 6r 37 10d 73 2c 2 6p 38 9e 74 3e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 5 7n 41 9c 77 1e 6 7r 42 9d 78 2f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 9 9r 45 9b 81 1f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 inte rnal notes: 1. nc pins as defined on the fbga ball assignments are read as dont c ares. 2. sta te of internal pin (#109) is loa ded via jtag
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 27 ordering information commercial range: 0c to +70c speed order part no. organization package 333 mhz is61qdb251236 a - 3 33 m3 512kx36 165 fbga (15x17 mm) IS61QDB251236A - 3 33 m3l 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 3 33 m3 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 3 33 m3l 1mx18 166 fbga (15x17 mm), lead free 300 mhz IS61QDB251236A - 300m3 512kx36 165 fbga (1 5x17 mm) IS61QDB251236A - 300m3l 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 300m3 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 300m3l 1mx18 165 fbga (15x17 mm), lead free 250 mhz IS61QDB251236A - 250 m3 512kx36 165 fbga (15x17 mm) IS61QDB251236A - 2 50 m3l 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 25 0m3 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 25 0m3l 1mx18 165 fbga (15x17 mm), lead free commercial range: 0c to +70c speed order part no. organization package 333 mhz IS61QDB251236A - 3 33 b4 512kx36 165 fbga (13x15 mm) IS61QDB251236A - 3 33 b4 l 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 3 33 b4 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 3 33 b4 l 1mx18 166 fbga (13x15 mm), lead free 300 mhz IS61QDB251236A - 30 0 b4 512kx36 165 fbga (13x15 mm) IS61QDB251236A - 30 0 b4 l 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 30 0 b4 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 30 0 b4 l 1mx18 165 fbga (13x15 mm), lead free 250 mhz IS61QDB251236A - 250 b4 512kx36 165 fbga (13x15 mm) IS61QDB251236A - 250 b4 l 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 250 b4 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 250 b4 l 1mx18 165 fbga (13x15 mm), lead free
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 28 industrial range: - 40c to +85c speed order part no. organization package 333 mhz IS61QDB251236A - 3 33 m3 i 512kx36 165 fbga (15x17 mm) IS61QDB251236A - 3 33 m3li 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 3 33 m3i 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 3 33 m3li 1mx18 165 fbga (15x17 mm), lead free 300 mhz IS61QDB251236A - 300m3i 512kx36 165 fbga (15x 17 mm) IS61QDB251236A - 300m3li 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 300m3i 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 300m3li 1mx18 165 fbga (15x17 mm), lead free 250 mhz IS61QDB251236A - 25 0m3i 512kx36 165 fbga (15x17 mm) IS61QDB251236A - 25 0m3li 512kx36 165 fbga (15x17 mm), lead free is61qdb21m18a - 25 0m3i 1mx18 165 fbga (15x17 mm) is61qdb21m18a - 25 0m3li 1mx18 165 fbga (15x17 mm), lead free industrial range: - 40c to +85c speed order part no. organization package 333 mhz is61qdb2512 36a - 3 3 3 b4 i 512kx36 165 fbga (13x15 mm) IS61QDB251236A - 3 3 3 b4 li 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 3 3 3 b4 i 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 3 3 3 b4 li 1mx18 165 fbga (13x15 mm), lead free 300 mhz IS61QDB251236A - 30 0 b4 i 512kx36 165 fbga (13x15 mm) IS61QDB251236A - 30 0 b4 li 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 30 0 b4 i 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 30 0 b4 li 1mx18 165 fbga (13x15 mm), lead free 250 mhz IS61QDB251236A - 250 b4 i 512kx36 165 fbga (13x15 mm) is61q db251236a - 250 b4 li 512kx36 165 fbga (13x15 mm), lead free is61qdb21m18a - 250 b4 i 1mx18 165 fbga (13x15 mm) is61qdb21m18a - 250 b4 li 1mx18 165 fbga (13x15 mm), lead free
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 29 package drawing C 1 5 x1 7 x1. 4 bga
is61qdb2 1 m18a is61qdb2 512 36a integrated silicon solution, inc. - www.issi.com rev. b 10/02/2014 30 package drawing C 13x15x1. 4 bga

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